A nonvolatile memory is a type of memory that retains stored data when power is removed. There are various types of nonvolatile memories including e.g., read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs), and flash memory.
Flash memory is often used where regular access to the data stored in the memory device is desired, but where such data is seldom changed. For example, computers often use flash memory to store firmware (e.g., a personal computer's BIOS). Peripheral devices such as printers may store fonts and forms on flash memory. Wireless communications devices such as cellular and other wireless telephones use flash memory to store data and their operating systems. Portable electronics such as digital cameras, audio recorders, personal digital assistants (PDAs), and test equipment use flash memory cards as a storage medium.
Flash memory cells make use of a floating-gate covered with an insulating layer. There is also a control gate which overlays the insulating layer. Below the floating gate is another insulating layer sandwiched between the floating gate and the cell substrate. This insulating layer is an oxide layer and is often referred to as the tunnel oxide. The substrate contains doped source and drain regions, with a channel region disposed between the source and drain regions. The floating-gate transistors generally include n-channel floating-gate field-effect transistors, but may also include p-channel floating-gate field-effect transistors. Access operations are carried out by applying biases to the transistor.
In a flash memory device, cells are often organized into blocks and the charge state of the floating gate indicates the logical state of the cell. For example, a charged floating gate may represent a logical “1” while a non-charged floating gate may represent a logical “0.” A flash memory cell may be programmed to a desired state by first erasing the cell to a logical “0” and, if necessary, writing the cell to a logical “1.” Typically, flash memory devices are organized so that a write operation can target a specific cell while an erase operation affects an entire block of cells. Changing any portion of one block therefore requires erasing the entire block and writing those bits in the block which correspond to a logical “1”.
Referring now to FIG. 1, a conventional flash memory cell 10 includes a source region 26 and a drain region 28. The source 26 and drain 28 have an N+ type conductivity formed in a P-type substrate 20. The memory cell 10 has a stack-gate configuration which includes a cap layer 22 formed over a control gate 18 formed over an insulating layer 16 formed over a floating gate 14 formed over a tunnel oxide layer 12. The floating gate 14 is formed of a first polysilicon layer and the control gate 18 is formed of a second polysilicon layer. The floating gate 14 is isolated from the control gate 18 by the insulating layer 16 and from a channel region 30 of the substrate 20 by the tunnel oxide layer 12. The tunnel oxide layer is generally about 100 Angstroms thick.
Referring now to FIG. 2, the conventional flash memory cell 10 is shown during a programming operation. A positive programming voltage Vp of, e.g., about 12 volts is applied to the control gate 18. The positive programming voltage Vp attracts electrons 32 from the P-type substrate 20 and causes them to accumulate at the surface of channel region 30. A voltage on drain 28 Vd is increased to, e.g., about 6 volts, and the source 26 is connected to ground Vs. As the drain-to-source voltage increases, electrons 32 flow from the source 26 to the drain 28 via channel region 30. As electrons 32 travel toward the drain 28, they acquire substantial high kinetic energy and are typically referred to as “hot” electrons.
The voltages at the control gate 18 and the drain 28 create an electric field in the oxide layer 12, which attracts the hot electrons and accelerates them toward the floating gate 14. At this point, the floating gate 14 begins to trap and accumulate the hot electrons. This is a charging process. As the charge on the floating gate 14 increases, the electric field in the oxide layer 12 decreases gradually and eventually loses its capability of attracting more hot electrons to the floating gate 14. At this point, the floating gate 14 is fully charged. The cell 10 will turn on when the voltage on the control gate 18 is brought to the threshold voltage level of the cell 10. Sense amplifiers are used in the memory to detect and amplify the state of the memory cell during a read operation.
Electrons are removed from the floating gate 14 to erase the memory cell. Fowler-Nordheim (FN) tunneling may be used to erase the memory cell 10. The erase procedure is accomplished by electrically floating the drain 28, grounding the source 26, and applying a high negative voltage (e.g., −12 volts) to the control gate 18. This creates an electric field across the tunnel oxide layer 12 and forces electrons off of the floating gate 14 and to then tunnel through the tunnel oxide layer 12 back to the substrate 20.
The erase operation requires high voltages and is relatively slow. The high erase voltages are a fundamental problem arising from the high electron affinity of bulk silicon or large grain polysilicon particles used as the floating gate. This creates a very high tunneling barrier. Even with high negative voltages applied to the gate, a large tunneling distance is experienced with a very low tunneling probability for electrons attempting to leave the floating gate. This results in long erase times since the net flux of electrons leaving the gate is low. Thus, the tunneling current discharging the gate is low. In addition, other phenomena result as a consequence of this very high negative voltage. Hole injection into the oxide is experienced which can result in erratic over erase, damage to the gate oxide itself, and the introduction of trapping states. Accordingly, there is a desire and need for a new flash memory cell architecture, which overcomes the aforementioned problems.